This invention relates to the fabrication of integrated circuits and in particular to a fabrication sequence for field effect transistors which permits reduced parasitics in the final devices.
With the continuing trend of greater numbers of components in integrated circuits and the need for high speed operation, increasing demands are made on field effect transistors. In particular, as channel lengths become shorter and junctions become shallower, increasing attention must be paid to the device parasitics to insure optimum performance of the transistors. For example, the source and drain junction capacitances and the series resistances between the channel and the contacts to the source and drain regions can significantly affect performance in short channel FETs. Also, when FETs are used as memory cells in dynamic random access memories, the output of a cell will depend inversely on the capacitance of the bit line. Consequently, a reduction in the bit line capacitance, which is the sum of the junction capacitances associated with that bit line, will significantly increase the speed of the memory. Junction capacitances can be reduced by decreasing the area of the source and drain regions. However, this also creates problems in aligning the contacts to these regions. Decreasing source and drain junction depths also increase the series resistance between the source and drain contacts and the channel. This resistance can be reduced by better alignment of the contacts so that they extend close to the channel region.
Other proposals for fabricating FETs have included deposition of a metal such as Pt onto the surfaces of the source and drain regions utilizing a gate electrode as a mask. The metal is then reacted with the exposed silicon to form metal silicide contacts and gates which are self-aligned. Unreacted metal over the silicon oxide (masking) areas is etched away without affecting the silicide. External contact is then provided by an aluminum metalization deposited onto a patterned insulating layer which includes openings over the source, drain and gate silicide regions (see, e.g., U.S. Pat. No. 4,319,395 issued to Lund et al and U.S. Pat. No. 4,343,082 issued to Lepselter et al). Although such techniques are adequate to reduce series resistance, they do not lend themselves easily to reductions in the area of source and drain regions since the openings in the insulating layer for external contact must be aligned within the source and drain areas. Further, direct contact of the silicide regions by the aluminum metal over the source and drain regions can result in spiking, which is a shorting of the junction caused by reaction of aluminum with the underlying silicon substrate. This problem is particularly acute for shallow junctions. In addition, for CMOS devices, where the metal layer must contact both n.sup.+ and p.sup.+ junction areas, there are additional constraints in that the metal should not affect the ohmic contact to either conductivity type regions.
Reduced source and drain areas will also aid in reducing the possibility of latchup in CMOS circuits. That is, increased separation is permitted between the adjacent edges of the n.sup.+ emitter in the p-type tub and the p.sup.+ emitter in the n-type tub without changing the layout area. Alternatively, smaller source and drain areas permit the layout area to be reduced while maintaining the separation of the adjacent edges of the same n.sup.+ and p.sup.+ emitters.
It is therefore a primary object of the invention to provide a method of producing small area, low capacitance source and drain regions with a means of contacting such regions so that the contacts are self-aligned with the gate electrode. It is a further object of the invention to provide contacts to the source and drain regions whih do not lead to spiking.